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Evidence Guide: UEEEC0054 - Provide gate array solutions for complex electronics systems

Student: __________________________________________________

Signature: _________________________________________________

Tips for gathering evidence to demonstrate your skills

The important thing to remember when gathering evidence is that the more evidence the better - that is, the more evidence you gather to demonstrate your skills, the more confident an assessor can be that you have learned the skills not just at one point in time, but are continuing to apply and develop those skills (as opposed to just learning for the test!). Furthermore, one piece of evidence that you collect will not usualy demonstrate all the required criteria for a unit of competency, whereas multiple overlapping pieces of evidence will usually do the trick!

From the Wiki University

 

UEEEC0054 - Provide gate array solutions for complex electronics systems

What evidence can you provide to prove your understanding of each of the following citeria?

Prepare to design gate array system

  1. Work health and safety (WHS)/occupational health and safety (OHS) requirements and workplace procedures for a given work area are identified and applied
Work health and safety (WHS)/occupational health and safety (OHS) requirements and workplace procedures for a given work area are identified and applied

Completed
Date:

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Operational safety procedures for a given work area are obtained and understood

Completed
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Extent of the proposed gate array system design and circuit development is determined from design brief or in consultation with appropriate person/s

Completed
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Design and circuit development work is planned to meet scheduled timelines in consultation with others involved

Completed
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Materials and devices/components required for the design work are selected on compatibility of their specifications with system requirements and project budget constraints

Completed
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Tools, equipment, software and testing devices needed to carry out the work are obtained and checked for correct operation and safety

Completed
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Design and develop circuit gate array system

  1. WHS/OHS risk control measures and workplace procedures for carrying out the design work are followed
WHS/OHS risk control measures and workplace procedures for carrying out the design work are followed

Completed
Date:

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Gate array system and industry compliance standards are applied to the design

Completed
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Alternative arrangements for the design and circuit development are considered in accordance with the requirements outlined in the design brief

Completed
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Safety, functional and budget considerations are incorporated in the design

Completed
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Circuit device and circuits are constructed and tested for compliance with the design brief and regulatory requirements

Completed
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Circuit malfunctions are rectified and retested to ensure effective operation with the design

Completed
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Gate array system design and development is documented for submission to appropriate person/s for approval

Completed
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Solutions to unplanned situations are provided in accordance with workplace policies

Completed
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Obtain approval for design and circuit development of gate array system and documentation

  1. Gate array system design is presented and explained to client representative and/or relevant person/s
Gate array system design is presented and explained to client representative and/or relevant person/s

Completed
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Requests for design modifications are negotiated with relevant person/s within the constraints of workplace policies

Completed
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Final design and circuit development are documented and approval obtained from appropriate person/s

Completed
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Quality of work is monitored against design brief, performance agreement and/or workplace procedures or industry standards

Completed
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Assessed

Teacher: ___________________________________ Date: _________

Signature: ________________________________________________

Comments:

 

 

 

 

 

 

 

 

Instructions to Assessors

Required Skills and Knowledge

Evidence required to demonstrate competence in this unit must be relevant to and satisfy all of the requirements of the elements, performance criteria and range of conditions on at least two separate occasions and include:

constructing, inspecting and testing circuit gate array device and circuits in accordance with design brief and regulatory requirements

dealing with unplanned situations in accordance with workplace procedures in a manner that minimises risk to personnel and equipment

designing gate array system in accordance with workplace procedures

developing outlines of alternative designs and comparing advantages and disadvantages on each

developing the gate array design within the safety and functional requirements and budget limitations

documenting and presenting design effectively

implementing relevant work health and safety (WHS)/occupational health and safety (OHS) requirements, including the use of risk control measures

negotiating design alteration requests and obtaining approval for final gate array design system

verifying compliance of the design against the final brief.

Evidence required to demonstrate competence in this unit must be relevant to and satisfy all of the requirements of the elements, performance criteria and range of conditions and include knowledge of:

gate array fundamentals

hardware design language

programmable logic device (PLD), including:

types of PLDs

features of complex programmable logic device (CPLD) devices

features of field programmable gate array (FPGA) devices

input/output (I/O) logic family assignment for FPGA

relevant job safety assessments or risk mitigation processes

relevant WHS/OHS legislated requirements

relevant workplace documentation

relevant workplace policies and procedures.

Range Statement

Range is restricted to essential operating conditions and any other variables essential to the work environment.

Non-essential conditions may be found in the UEE Electrotechnology Training Package Companion Volume Implementation Guide.

Designing and developing a gate array system must include at least the following:

three input/output (I/O) devices or functions